MIPS RISC architectures
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
Division Algorithms and Implementations
IEEE Transactions on Computers
Numerical computing with IEEE floating point arithmetic
Numerical computing with IEEE floating point arithmetic
Advanced Computer Arithmetic Design
Advanced Computer Arithmetic Design
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
FPGAs vs. CPUs: trends in peak floating-point performance
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Single Pass, BLAST-Like, Approximate String Matching on FPGAs
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
Architectural modifications to enhance the floating-point performance of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware Compilation from Machine Code with M2V
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Flexible multi-mode embedded floating-point unit for field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
FPGA Floating Point Datapath Compiler
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Floating-point FPGA: architecture and modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Multimedia and communication algorithms from the embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-point hardware, these algorithms are usually converted to fixed point operations, or implemented using floating-point emulation in software. This study presents the design and implementation of custom floating-point units, leveraging the partial reconfiguration feature of state-of-the-art FPGAs. The custom floating-point units can be dynamically configured, loaded, and executed when needed by software applications. The system is binary compliant with the conventional MIPS architecture and the IEEE-754 standard, and supports most of the floating-point operations and relevant functionalities. Furthermore, we investigate various customization strategies and construct a set of optimized functional modules to meet different application demands or requirements. Using LINPACK as a floating-point intensive example, we replace a sequence of 25 instructions with a custom unit, and demonstrate an overall 80x application speedup.