the LINPACK benchmark: an explanation
Proceedings of the 1st International Conference on Supercomputing
Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
IEEE Transactions on Computers
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Automating Customisation of Floating-Point Designs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Library of Parameterized Floating-Point Modules and Their Use
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An empirical performance evaluation of scalable scientific applications
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Floating Point Unit Generation and Evaluation for FPGAs
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Floating-point sparse matrix-vector multiply for FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
64-bit floating-point FPGA matrix multiplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Embedded floating-point units in FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Architectures and APIs: assessing requirements for delivering FPGA performance to applications
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
Optimized high-order finite difference wave equations modeling on reconfigurable computing platform
Microprocessors & Microsystems
Automatic mapping of nested loops to FPGAS
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
Coprocessor design to support MPI primitives in configurable multiprocessors
Integration, the VLSI Journal
Examining the viability of FPGA supercomputing
EURASIP Journal on Embedded Systems
An Accelerator for Physics Simulations
Computing in Science and Engineering
High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs
IEEE Transactions on Parallel and Distributed Systems
Journal of Parallel and Distributed Computing
Architectural modifications to enhance the floating-point performance of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Multiplier-Based Double Precision Floating Point Divider According to the IEEE-754 Standard
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Floating-point divider design for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Parameterizable floating-point library for arithmetic operations in FPGAs
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
A network-centric approach to space-restricted distributed processing
Microprocessors & Microsystems
A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer with Application
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Reconfigurable custom floating-point instructions (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Searching the web with an FPGA based search engine
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Fast, Efficient Floating-Point Adders and Multipliers for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Implementation of hardware-accelerated scalable parallel random number generators
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Rapid development of high performance floating-point pipelines for scientific simulation
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Multipliers for floating-point double precision and beyond on FPGAs
ACM SIGARCH Computer Architecture News
Domain-Specific Optimization of Signal Recognition Targeting FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA implementation of variable-precision floating-point arithmetic
APPT'11 Proceedings of the 9th international conference on Advanced parallel processing technologies
The "Chimera": an off-the-shelf CPU/GPGPU/FPGA hybrid computing platform
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
FPGA paranoia: testing numerical properties of FPGA floating point IP-Cores
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Journal of Parallel and Distributed Computing
Floating-Point Exponentiation Units for Reconfigurable Computing
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The Journal of Supercomputing
Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier
Microprocessors & Microsystems
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Moore's Law states that the number of transistors on a device doubles every two years; however, it is often (mis)quoted based on its impact on CPU performance. This important corollary of Moore's Law states that improved clock frequency plus improved architecture yields a doubling of CPU performance every 18 months. This paper examines the impact of Moore's Law on the peak floating-point performance of FPGAs. Performance trends for individual operations are analyzed as well as the performance trend of a common instruction mix (multiply accumulate). The important result is that peak FPGA floating-point performance is growing significantly faster than peak floating-point performance for a CPU.