Floating Point Unit Generation and Evaluation for FPGAs

Authors:
Jian Liang;Russell Tessier;Oskar Mencer
Affiliations:
-;-;-
Venue:
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2003

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Abstract

Most commercial and academic floating point librariesfor FPGAs provide only a small fraction of all possiblefloating point units. In contrast, the floating point unit generationapproach outlined in this paper allows for the creationof a vast collection of floating point units with differingthroughput, latency, and area characteristics. Givenperformance requirements, our generation tool automaticallychooses the proper implementation algorithm and architectureto create a compliant floating point unit. Ourapproach is fully integrated into standard C++ using ASC,a stream compiler for FPGAs, and the PAM-Blox II modulegeneration environment. The floating point units created byour approach exhibit a factor of two latency improvementversus commercial FPGA floating point units, while consumingonly half of the FPGA logic area.