Word length selection method for controller implementation on FPGAs using the VHDL-2008 fixed-point and floating-point packages

Authors:
I. Urriza;L. A. Barragán;D. Navarro;J. I. Artigas;O. Lucia
Affiliations:
Departamento de Ingeniería Electrónica y Comunicciones, Universidad de Zaragoza, Zaragoza, Spain;Departamento de Ingeniería Electrónica y Comunicciones, Universidad de Zaragoza, Zaragoza, Spain;Departamento de Ingeniería Electrónica y Comunicciones, Universidad de Zaragoza, Zaragoza, Spain;Departamento de Ingeniería Electrónica y Comunicciones, Universidad de Zaragoza, Zaragoza, Spain;Departamento de Ingeniería Electrónica y Comunicciones, Universidad de Zaragoza, Zaragoza, Spain
Venue:
EURASIP Journal on Embedded Systems
Year:
2010

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Abstract

This paper presents a word length selection method for the implementation of digital controllers in both fixed-point and floating-point hardware on FPGAs. This method uses the new types defined in the VHDL-2008 fixed-point and floating-point packages. These packages allow customizing the word length of fixed and floating point representations and shorten the design cycle simplifying the design of arithmetic operations. The method performs bit-true simulations in order to determine the word length to represent the constant coefficients and the internal signals of the digital controller while maintaining the control system specifications. A mixed-signal simulation tool is used to simulate the closed loop system as a whole in order to analyze the impact of the quantization effects and loop delays on the control system performance. The method is applied to implement a digital controller for a switching power converter. The digital circuit is implemented on an FPGA, and the simulations are experimentally verified.