Customisable Hardware Compilation
The Journal of Supercomputing
MP core: algorithm and design techniques for efficient channel estimation in wireless applications
Proceedings of the 42nd annual Design Automation Conference
MiniBit: bit-width optimization via affine arithmetic
Proceedings of the 42nd annual Design Automation Conference
Word-length optimization for differentiable nonlinear systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A stochastic bitwidth estimation technique for compact and low-power custom processors
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 45th annual Design Automation Conference
International Journal of Parallel, Emergent and Distributed Systems
Scenario-based fixed-point data format refinement to enable energy-scalable software defined radios
Proceedings of the conference on Design, automation and test in Europe
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A java simulation tool for fixed-point system design
Proceedings of the 2nd International Conference on Simulation Tools and Techniques
Custom floating-point unit generation for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Fast trade-off evaluation for digital signal processing systems during wordlength optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Bit-width allocation for hardware accelerators for scientific computing using SAT-modulo theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting finite precision information to guide data-flow mapping
Proceedings of the 47th Design Automation Conference
Robust design methods for hardware accelerators for iterative algorithms in scientific computing
Proceedings of the 47th Design Automation Conference
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Tradeoff between Approximation Accuracy and Complexity for Range Analysis using Affine Arithmetic
Journal of Signal Processing Systems
SQNR estimation of fixed-point DSP algorithms
EURASIP Journal on Advances in Signal Processing
EURASIP Journal on Embedded Systems
Trustworthy numerical computation in Scala
Proceedings of the 2011 ACM international conference on Object oriented programming systems languages and applications
Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits
Proceedings of the International Conference on Computer-Aided Design
Multi-level customisation framework for curve based monte carlo financial simulations
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Optimising performance of quadrature methods with reduced precision
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
International Journal of Computational Science and Engineering
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This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation to compute the sensitivities of outputs to the bit-width of the various operands in the design. This sensitivity analysis enables us to explore and compare fixed-point and floating-point implementation for a particular design. As a result we can automate the selection of the optimal number representation for each variable in a design to optimize area and performance. We implement our method in the BitSize tool targeting reconfigurable architectures, which takes user-defined constraints to direct the optimisation procedure. We illustrate our approach using applications such as ray-tracing and function approximation.