MP core: algorithm and design techniques for efficient channel estimation in wireless applications

Authors:
Yan Meng;Andrew P. Brown;Ronald A. Iltis;Timothy Sherwood;Hua Lee;Ryan Kastner
Affiliations:
University of California, Santa Barbara, Santa Barbara, CA;University of California, Santa Barbara, Santa Barbara, CA;University of California, Santa Barbara, Santa Barbara, CA;University of California, Santa Barbara, Santa Barbara, CA;University of California, Santa Barbara, Santa Barbara, CA;University of California, Santa Barbara, Santa Barbara, CA
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

Citing 13
Cited 5

Bidwidth analysis with application to silicon compilation

PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
MetaCores: design and optimization techniques

Proceedings of the 38th annual Design Automation Conference
Multiuser Detection

Multiuser Detection
Synthesis and Optimization of Digital Circuits

Synthesis and Optimization of Digital Circuits
A Survey of Digital Design Reuse

IEEE Design & Test
A Library of Parameterized Floating-Point Modules and Their Use

FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
High-level synthesis of distributed logic-memory architectures

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs

FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Multipath time-delay detection and estimation

IEEE Transactions on Signal Processing
Geometric derivation of expectation-maximization and generalized successive interference cancellation algorithms with applications to CDMA channel estimation

IEEE Transactions on Signal Processing
Real-time algorithms and architectures for multiuser channel estimation and detection in wireless base-station receivers

IEEE Transactions on Wireless Communications
Bitwidth cognizant architecture synthesis of custom hardware accelerators

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Leakage power reduction of embedded memories on FPGAs through location assignment

Proceedings of the 43rd annual Design Automation Conference
Survey of hardware platforms for an energy efficient implementation of matching pursuits algorithm for shallow water networks

Proceedings of the third ACM international workshop on Underwater Networks
Architectural optimization of decomposition algorithms for wireless communication systems

WCNC'09 Proceedings of the 2009 IEEE conference on Wireless Communications & Networking Conference
GUSTO: An automatic generation and optimization tool for matrix inversion architectures

ACM Transactions on Embedded Computing Systems (TECS)
Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs

International Journal of Reconfigurable Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Channel estimation and multiuser detection are enabling technologies for future generations of wireless applications. However, sophisticated algorithms are required for accurate channel estimation and multiuser detection, and real-time implementation of these algorithms is difficult. This paper presents architectural design methods for wireless channel estimation which can be leveraged to enable real-time multiuser detection. We redesign the matching pursuit (MP) channel estimation algorithm to reduce the complexity while maintaining the estimation accuracy. Furthermore, we develop a parameterized intellectual property (IP) core, which provides a hardware implementation of the MP algorithm. Experimental results demonstrate the effectiveness and ef- ficiency of the new algorithm and IP core for channel estimation. The implementation of our MP core on a modern, high performance reconfigurable system is about 216 times faster than running the algorithm on a state of the art microprocessor. The MP core possesses the speed required for performing true multiuser detection, enabling future generations of wireless communication applications.