Discrete-time signal processing
Discrete-time signal processing
Symbolic and knowledge-based signal processing
Symbolic and knowledge-based signal processing
Virtual simulation of distributed IP-based designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hardware reuse at the behavioral level
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Program developments: formal explanations of implementations
Communications of the ACM
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
Algorithm selection: a quantitative optimization-intensive approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MP core: algorithm and design techniques for efficient channel estimation in wireless applications
Proceedings of the 42nd annual Design Automation Conference
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Currently, hardware intellectual property (IP) is delivered at three levels of abstraction: hard, firm, and soft. In order to further enhance performance, efficiency, and flexibility of IP design, we have developed a new approach for designing hardware and software IP called MetaCores. The new design approach starts at the algorithm level and leverages on the algorithms intrinsic optimization degrees of freedom. The approach has four main components: (i) problem formulation and identification of optimization degrees of freedom, (ii) objective functions and constraints, (iii) cost evaluation engine, and (iv) multiresolution design space search. From the algorithmic viewpoint, the main contribution is the introduction of multiresolution search in algorithm optimization and synthesis process. We have applied the approach to the development of Viterbi and IIR MetaCores. Experimental results demonstrate the effectiveness of the new approach.