REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
C language algorithms for digital signal processing
C language algorithms for digital signal processing
An O(nlogn) algorithm for finding minimal path cover in circular-arc graphs
CSC '93 Proceedings of the 1993 ACM conference on Computer science
Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
On the Limits of Leakage Power Reduction in Caches
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
MP core: algorithm and design techniques for efficient channel estimation in wireless applications
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Banked scratch-pad memory management for reducing leakage energy consumption
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power modeling and characteristics of field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
Transistor leakage is poised to become the dominant source of power dissipation in digital systems, and reconfigurable devices are not immune to this problem. Modern FPGAs already have a significant amount of memory on the die, and with each generation the proportion of embedded memory to logic cells is growing. While assigning high Vth can limit the leakage power, embedded memory timing is critical to performance and will draw an increasingly significant amount of leakage current. However, unlike in many processor based systems, on-chip memory accesses are often fully deterministic and completely under the control of the scheduler. In this paper we explore a variety of techniques to battle the problem of leakage in FPGA embedded memories that range in complexity and effectiveness. Through the addition of sleep and drowsy modes, controlled by the scheduler, the amount of leakage power can be reduced by several orders of magnitude. We show how even very simple schemes offer large amounts of benefit, and that further reductions are possible through careful leakage-aware data placement.