Banked scratch-pad memory management for reducing leakage energy consumption

Authors:
M. Kandemir;M. J. Irwin;G. Chen;I. Kolcu
Affiliations:
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA;Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA;Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA;Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., PA, USA
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

Citing 8
Cited 4

Cache decay: exploiting generational behavior to reduce cache leakage power

ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Exploiting shared scratch pad memory space in embedded multiprocessor systems

Proceedings of the 39th annual Design Automation Conference
Drowsy caches: simple techniques for reducing leakage power

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Design of High-Performance Microprocessor Circuits

Design of High-Performance Microprocessor Circuits
Efficient Algorithms for Array Redistribution

IEEE Transactions on Parallel and Distributed Systems
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction

Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications

EDTC '97 Proceedings of the 1997 European conference on Design and Test
Assigning Program and Data Objects to Scratchpad for Energy Reduction

Proceedings of the conference on Design, automation and test in Europe

Leakage power reduction of embedded memories on FPGAs through location assignment

Proceedings of the 43rd annual Design Automation Conference
Compiler-guided leakage optimization for banked scratch-pad memories

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems

Journal of Electronic Testing: Theory and Applications
Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors

ACM Transactions on Embedded Computing Systems (TECS)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. We propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into low-power (low-leakage) state.