Compiler-guided leakage optimization for banked scratch-pad memories

Authors:
Mahmut Kandemir;Mary Jane Irwin;Guilin Chen;Ibrahim Kolcu
Affiliations:
Computer Science and Engineering Department, The Pennsylvania State University, University Park, PA;Computer Science and Engineering Department, The Pennsylvania State University, University Park, PA;Computer Science and Engineering Department, The Pennsylvania State University, University Park, PA;Computation Department, University of Manchester, Manchester, U.K
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

Current trends indicate that leakage energy consumption will be an important concern in upcoming process technologies. In this paper, we propose a compiler-based leakage energy optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to divide SPM into banks and use compiler-guided memory-data layout optimization and data migration to maximize SPM bank idleness, thereby increasing the chances of placing banks into a low-power (low-leakage) state. Our experimental results with eight applications show that the proposed compiler-based strategy is very effective in reducing leakage energy of on-chip SPMs.