A low power SRAM using auto-backgate-controlled MT-CMOS
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Dynamic fine-grain leakage reduction using leakage-biased bitlines
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Reducing set-associative cache energy via way-prediction and selective direct-mapping
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Predictive sequential associative cache
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Static Energy Reduction Techniques for Microprocessor Caches
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Exploiting program hotspots and code sequentiality for instruction cache leakage management
Proceedings of the 2003 international symposium on Low power electronics and design
Tracking object life cycle for leakage energy optimization
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Low Static-Power Frequent-Value Data Caches
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Reducing instruction cache energy consumption using a compiler-based strategy
ACM Transactions on Architecture and Code Optimization (TACO)
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Controlling leakage power with the replacement policy in slumberous caches
Proceedings of the 2nd conference on Computing frontiers
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Proceedings of the 2nd conference on Computing frontiers
Snug set-associative caches: reducing leakage power while improving performance
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Exploring the limits of leakage power reduction in caches
ACM Transactions on Architecture and Code Optimization (TACO)
Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows
Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Banked scratch-pad memory management for reducing leakage energy consumption
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Low-leakage robust SRAM cell design for sub-100nm technologies
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
STV-Cache: a leakage energy-efficient architecture for data caches
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Memory management challenges in the power-aware computing era
Proceedings of the 5th international symposium on Memory management
Minimizing energy consumption of banked memories using data recomputation
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 20th annual international conference on Supercomputing
Evaluating trace cache energy efficiency
ACM Transactions on Architecture and Code Optimization (TACO)
ACM Transactions on Architecture and Code Optimization (TACO)
Trace-based leakage energy optimisations at link time
Journal of Systems Architecture: the EUROMICRO Journal
Exploiting loop behavior for data cache leakage reduction
Journal of Embedded Computing - Cache exploitation in embedded systems
Reducing branch predictor leakage energy by exploiting loops
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Addressing instruction fetch bottlenecks by using an instruction register file
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Locality-driven architectural cache sub-banking for leakage energy reduction
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Cache leakage control mechanism for hard real-time systems
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Reducing leakage in power-saving capable caches for embedded systems by using a filter cache
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Analysis of static and dynamic energy consumption in NUCA caches: initial results
MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture
Filtering drowsy instruction cache to achieve better efficiency
Proceedings of the 2008 ACM symposium on Applied computing
Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Capturing and optimizing the interactions between prefetching and cache line turnoff
Microprocessors & Microsystems
Case study of reliability-aware and low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems
Transactions on High-Performance Embedded Architectures and Compilers I
Hardware-compiler co-design for adjustable data power savings
Microprocessors & Microsystems
A DVS-based pipelined reconfigurable instruction memory
Proceedings of the 46th Annual Design Automation Conference
Low Vccmin fault-tolerant cache with highly predictable performance
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Cache partitioning for energy-efficient and interference-free embedded multitasking
ACM Transactions on Embedded Computing Systems (TECS)
Reuse distance based cache leakage control
HiPC'07 Proceedings of the 14th international conference on High performance computing
Cryptographic side-channels from low-power cache memory
Cryptography and Coding'07 Proceedings of the 11th IMA international conference on Cryptography and coding
Stacking SRAM banks for ultra low power standby mode operation
Proceedings of the 47th Design Automation Conference
Power and performance aware reconfigurable cache for CMPs
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies
Compiler-guided leakage optimization for banked scratch-pad memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantitative analysis and optimization techniques for on-chip cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Saving register-file static power by monitoring instruction sequence in ROB
Journal of Systems Architecture: the EUROMICRO Journal
Trace-Based data cache leakage reduction at link time
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
On the reliability of drowsy instruction caches
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
An adaptive technique for reducing leakage and dynamic power in register files and reorder buffers
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
An innovative instruction cache for embedded processors
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
FPGAs for improved energy efficiency in processor based systems
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Cache leakage management for multi-programming workloads
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Link-time optimization for power efficiency in a tagless instruction cache
CGO '11 Proceedings of the 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization
A novel power-gating scheme utilizing data retentiveness on caches
Proceedings of the great lakes symposium on VLSI
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
A survey on cache tuning from a power/energy perspective
ACM Computing Surveys (CSUR)
Leakage energy estimates for HPC applications
E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
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On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. In our previous work we have shown how the drowsy circuit---a simple, state-preserving, low-leakage circuit that relies on voltage scaling for leakage reduction---can be used to reduce the total energy consumption of data caches by more than 50%. In this paper, we extend the architectural control mechanism of-the drowsy cache to reduce leakage power consumption of instruction caches without significant impact on execution time. Our results show that data and instruction caches require different control strategies for efficient execution. To enable drowsy instruction caches, we propose a technique called cache subbank prediction which is used to selectively wake up only the necessary parts of the instruction cache, while allowing most of the cache to stay in a low leakage drowsy mode. This prediction technique reduces the negative performance impact by 76% compared to the no-prediction policy. Our technique works well even with small predictor sizes and enables an 86% reduction of leakage energy in a 64K byte instruction cache.