ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Analysis of dual-Vt SRAM cells with full-swing single-ended bit line sensing for on-chip cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DRG-cache: a data retention gated-ground cache for low power
Proceedings of the 39th annual Design Automation Conference
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Low-leakage asymmetric-cell SRAM
Proceedings of the 2002 international symposium on Low power electronics and design
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Analyzing Soft Errors in Leakage Optimized SRAM Design
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Design Techniques for Gate-Leakage Reduction in CMOS Circuits
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
A forward body-biased low-leakage SRAM cache: device and architecture considerations
Proceedings of the 2003 international symposium on Low power electronics and design
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
Proceedings of the conference on Design, automation and test in Europe - Volume 1
The Effect of Threshold Voltages on the Soft Error Rate
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design and analysis of two low-power SRAM cell structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel low-leakage robust SRAM design for sub-100nm technologies, Hybrid SRAM (HSRAM) cell, is presented in this paper. Leakage power, especially subthreshold leakage and gate leakage, and soft error are challenging the design of SRAM. While these important issues have been separately addressed in previous SRAM designs, there exists no design that simultaneously cuts down leakage power and enhances the resistance to soft error. In this work, we have built the first such SRAM cell, by hybrid of high-k gate dielectric and dynamic threshold voltage which is realized in the form of jointly biased gate and substrate transistor. The HSRAM not only makes the gate leakage negligible, but lessens the severe increase of subthreshold leakage caused by Fringing/Field Induced Barrier Lowering (FIBL) effect accompanied with the introduction of high-k gate dielectric, and in the same time reduces the susceptibility to soft error by increasing the node capacitance. Experiments were performed in both transistor level and circuit level for this novel HSRAM using ISE8.0 and HSPICE. They indicate that up to 93% reduction in total leakage is possible by using HSRAM cell, with an up to 23% increase in reliability degree and and an up to 73% reduction in bitline delay, compared to standard 6T SRAM.