Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
An Asymmetric SRAM Cell to Lower Gate Leakage
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Low-leakage robust SRAM cell design for sub-100nm technologies
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A low-power SRAM using bit-line charge-recycling technique
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Characterization of a novel nine-transistor SRAM cell
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memristor based programmable threshold logic array
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology
Wireless Personal Communications: An International Journal
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In this paper, two static random access memory (SRAM) cells that reduce the static power dissipation due to gate and subthreshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation.