A low-power SRAM using bit-line charge-recycling technique

Authors:
Keejong Kim;Hamid Mahmoodi;Kaushik Roy
Affiliations:
Purdue University;San Francisco State University;Purdue University
Venue:
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Year:
2007

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Abstract

We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance. In order to improve the data retention capability of un-selected cells during write, the power supply lines of memory cells in one column are connected to each other and separated from the power lines of other columns. A test-chip is fabricated in 0.13μm CMOS and measurement results show 88% reduction in total power compared to the conventional SRAM (CON-SRAM) at VDD=1.5V and f=100MHz.