Practical low-cost CPL implementations threshold logic functions
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A circuit-software co-design approach for improving EDP in reconfigurable frameworks
Proceedings of the 2009 International Conference on Computer-Aided Design
Design and analysis of two low-power SRAM cell structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
How We Found The Missing Memristor
IEEE Spectrum
VLSI implementations of threshold logic-a comprehensive survey
IEEE Transactions on Neural Networks
Non linear dynamics of memristor based 3rd order oscillatory system
Microelectronics Journal
Memristor PUFs: a new generation of memory-based physically unclonable functions
Proceedings of the Conference on Design, Automation and Test in Europe
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In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.