Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Hierarchical Probabilistic Macromodeling for QCA Circuits
IEEE Transactions on Computers
Reconfigurable RTD-based circuit elements of complete logic functionality
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Automatic test generation for combinational threshold logic networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Memristor based programmable threshold logic array
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
On rewiring and simplification for canonicity in threshold logic circuits
Proceedings of the International Conference on Computer-Aided Design
Design tools for artificial nervous systems
Proceedings of the 49th Annual Design Automation Conference
Minimizing area and power of sequential CMOS circuits using threshold decomposition
Proceedings of the International Conference on Computer-Aided Design
Exploring Boolean and non-Boolean computing with spin torque devices
Proceedings of the International Conference on Computer-Aided Design
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We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and research on thedevelopment of synthesis methodologies to generate optimized networks utilizing these devices. Many nanotechnologies, such as resonant tunneling diodes (RTD) and quantum cellular automata (QCA), are capable of implementing threshold logic. While functionally correct threshold gates have been successfully demonstrated, there exists no methodology or design automation tool for general multi-level threshold network synthesis. We have built the first such tool, ThrEshold Logic Synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with about 60 multi-output benchmarks were performed, though the results of only 10 of them are reported in this paper because of space restrictions. They indicate that up to 77% reduction in gate count is possible when utilizing threshold logic, with an average reduction being 52%, compared to traditional logic synthesis. Furthermore, thesynthesized networks are well-balanced, and hence delay-optimized.