BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Maximum weighted independent sets on transitive graphs and applications
Integration, the VLSI Journal
Small Maximal Independent Sets and Faster Exact Graph Coloring
WADS '01 Proceedings of the 7th International Workshop on Algorithms and Data Structures
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies
Proceedings of the conference on Design, automation and test in Europe - Volume 2
VLSI implementations of threshold logic-a comprehensive survey
IEEE Transactions on Neural Networks
Identification of Threshold Functions and Synthesis of Threshold Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes the design of a standard cell library of differential mode threshold gates, referred to as a Threshold Logic Latch or TLL, and new threshold function identification and decomposition methods to map a conventional logic network consisting of logic gates and flipflops, into a hybrid network that consists of both TLLs and conventional logic gates. After logic synthesis and physical design (placement and routing) using a commercial 65nm LP (low power) library, and commercial design tools, the hybrid circuits are shown to have up to 35% less dynamic power, about 50% less leakage power and around 37% less area when compared to the corresponding conventional design operated at the same (peak) frequency.