BDD based decomposition of logic functions with application to FPGA synthesis

Optimum functional decomposition using encoding

DAC '94 Proceedings of the 31st annual Design Automation Conference

A new power estimation technique with application to decomposition of Boolean functions for low power

EURO-DAC '94 Proceedings of the conference on European design automation

Simultaneous depth and area minimization in LUT-based FPGA mapping

FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays

Functional multiple-output decomposition: theory and an implicit algorithm

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

A method for finding good Ashenhurst decompositions and its application to FPGA synthesis

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

RASP: a general logic synthesis system for SRAM-based FPGAs

Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays

Combinational logic synthesis for LUT based field programmable gate arrays

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs

DAC '96 Proceedings of the 33rd annual Design Automation Conference

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Partially-dependent functional decomposition with applications in FPGA synthesis and mapping

FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

FGILP: an integer linear program solver based on function graphs

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

Low power FPGA design—a re-engineering approach

DAC '97 Proceedings of the 34th annual Design Automation Conference

Finding all simple disjunctive decompositions using irredundant sum-of-products forms

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Constructive library-aware synthesis using symmetries

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Multi-output functional decomposition with exploitation of don't cares

Proceedings of the conference on Design, automation and test in Europe

Restructuring logic representations with easily detectable simple disjunctive decompositions

Proceedings of the conference on Design, automation and test in Europe

An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Multi-level logic optimization

Logic Synthesis and Verification

BDD-based logic synthesis for LUT-based FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Formal Verification Using Edge-Valued Binary Decision Diagrams

IEEE Transactions on Computers

Function Decomposition in Machine Learning

Machine Learning and Its Applications, Advanced Lectures

Resynthesis of multi-level circuits under tight constraints using symbolic optimization

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

A new enhanced constructive decomposition and mapping algorithm

Proceedings of the 40th annual Design Automation Conference

An Implicit Algorithm for Support Minimization during Functional Decomposition

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Minimizing ROBDD Sizes of Incompletely Specified Boolean Functions by Exploiting Strong Symmetries

EDTC '97 Proceedings of the 1997 European conference on Design and Test

LUT-based FPGA Technology Mapping using Permissible Functions

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Effective and efficient FPGA synthesis through general functional decomposition

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems

A method to decompose multiple-output logic functions

Proceedings of the 41st annual Design Automation Conference

General decomposition of incompletely specified sequential machines with multi-state behavior realization

Journal of Systems Architecture: the EUROMICRO Journal

An efficient algorithm for finding the minimal-area FPGA technology mapping

ACM Transactions on Design Automation of Electronic Systems (TODAES)

BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition

Proceedings of the 42nd annual Design Automation Conference

Information-driven circuit synthesis with the pre-characterized gate libraries

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application

Efficient LUT-based FPGA technology mapping for power minimization

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Detecting support-reducing bound sets using two-cofactor symmetries

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

An efficient variable partitioning approach for functional decomposition of circuits

Journal of Systems Architecture: the EUROMICRO Journal

Functionally linear decomposition and synthesis of logic circuits for FPGAs

Proceedings of the 45th annual Design Automation Conference

BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

A relational approach to functional decomposition of logic circuits

ACM Transactions on Database Systems (TODS)

Computing support-minimal subfunctions during functional decomposition

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

New & improved models for SAT-based bi-decomposition

Proceedings of the great lakes symposium on VLSI

Minimizing area and power of sequential CMOS circuits using threshold decomposition

Proceedings of the International Conference on Computer-Aided Design