Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Field-programmable gate arrays
Field-programmable gate arrays
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Area and delay mapping for table-look-up based field programmable gate arrays
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
FPGA Technology Mapping for Power Minimization
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
GlitchMap: an FPGA technology mapper for low power considering glitches
Proceedings of the 44th annual Design Automation Conference
Technology mapping and clustering for FPGA architectures with dual supply voltages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SETmap: a soft error tolerant mapping algorithm for FPGA designs with low power
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Sa based power efficient FPGA LUT mapping
Proceedings of the 15th annual conference companion on Genetic and evolutionary computation
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We study the technology mapping problem for LUT-based FPGAs targeting at power minimization. The problem has been proved to be NP-hard previously. Hence, we present an efficient heuristic to compute low-power mapping solutions. The major distinction of our work from previous ones is that while generating a LUT, we look ahead at the impact of the mapping selection of this LUT on the power consumption of the remaining network. We choose the mapping that results in the least estimated overall power consumption. The key idea is to compute low-power K-feasible cuts by an efficient incremental network flow computation method. Experimental results show that our algorithm reduces both power consumption and area over the previous algorithms reported in the literature.