The complexity of Boolean functions
The complexity of Boolean functions
Low power FPGA design—a re-engineering approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
In-place power optimization for LUT-based FPGAs
DAC '98 Proceedings of the 35th annual Design Automation Conference
A re-engineering approach to low power FPGA design using SPFD
DAC '98 Proceedings of the 35th annual Design Automation Conference
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
FPGA Technology Mapping for Power Minimization
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient LUT-based FPGA technology mapping for power minimization
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Power-aware FPGA logic synthesis using binary decision diagrams
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Power-aware, depth-optimum and area minimization mapping of K-LUT based FPGA circuits
WSEAS Transactions on Computers
A 90-nm Low-Power FPGA for Battery-Powered Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Complexity of the lookup-table minimization problem for FPGA technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Look up Table (LUT) based Field Programmable Gate Arrays (FPGAs) are commonly used in mobile devices due to their efficient signal processing capabilities and flexibility to be reprogrammed in situ. However the mechanisms which enable a FPGA to be re-programmable make it require more power than an Application Specific Integrated Circuit. In this paper we consider the power reduction of a FPGA by optimising the mapping the underlying boolean circuit onto the LUT based FPGA with respect to cumulative switching. We formulate the power minimisation problem as a combinatorial optimisation problem. To tackle this NP hard problem we propose the application of a local search method. Here we introduce a complete a neighborhood function and apply heuristic simulated annealing in conjunction with the objective function from [20] 'cumulative switching'. Our experimental results show a 42.96% average reduction in power consumption compared to SIS based mapping and 27.44% average reduction in power consumption compared to a genetic algorithm.