Field-programmable gate arrays
Field-programmable gate arrays
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Low power FPGA design—a re-engineering approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
Logic transformation for low power synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Power and delay reduction via simultaneous logic and placement optimization in FPGAs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Logic transformation for low-power synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A new enhanced SPFD rewiring algorithm
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Proceedings of the 47th Design Automation Conference
Switching-Activity directed clustering algorithm for low net-power implementation of FPGAs
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Sa based power efficient FPGA LUT mapping
Proceedings of the 15th annual conference companion on Genetic and evolutionary computation
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In this paper, we present a method to re-synthesize Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) for low power design after technology mapping, placement and routing are performed. We use Set of Pairs of Functions to be Distinguished (SPFD) to express functional permissibility of each signal. Using different propagations of SPFD to fan-in signals, we change the functionality of a PLB (Programmable Logic Block) which drives large loading into one with low transition density. Experimental results show that our method can reduce on average 12% power consumption compared to the original circuits without affecting placement and routing.