A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Guarded evaluation: pushing power management to logic synthesis/design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An exact algorithm for low power library-specific gate re-sizing
DAC '96 Proceedings of the 33rd annual Design Automation Conference
State assignment for FSM low power design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Scheduling for power reduction in a real-time system
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Power management techniques for control-flow intensive designs
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
A re-engineering approach to low power FPGA design using SPFD
DAC '98 Proceedings of the 35th annual Design Automation Conference
Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Transforming control-flow intensive designs to facilitate power management
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Low-Power Design for Real-Time Systems
Real-Time Systems
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A bipartition-codec architecture to reduce power in pipelined circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
New clock-gating techniques for low-power flip-flops
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ACM Transactions on Computer Systems (TOCS)
Gated clock routing minimizing the switched capacitance
Proceedings of the conference on Design, automation and test in Europe
FSM decomposition by direct circuit manipulation applied to low power design
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Input space adaptive design: a high-level methodology for energy and performance optimization
Proceedings of the 38th annual Design Automation Conference
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Retiming-based logic synthesis for low-power
Proceedings of the 2002 international symposium on Low power electronics and design
Logic Synthesis and Verification
A survey of design techniques for system-level dynamic power management
Readings in hardware/software co-design
Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications
Wireless Personal Communications: An International Journal
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
FSM Decomposition for Low Power in FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Compiler optimization on VLIW instruction scheduling for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A novel architecture for power maskable arithmetic units
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A low-power adder operating on effective dynamic data ranges
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
Energy-aware design techniques for differential power analysis protection
Proceedings of the 40th annual Design Automation Conference
Optimization of combinational and sequential logic circuits for low power using precomputation
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Design for Testability of Gated-Clock FSMs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Low power FSM design using Huffman-style encoding
EDTC '97 Proceedings of the 1997 European conference on Design and Test
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Dynamic Functional Unit Assignment for Low Power
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Input space adaptive design: a high-level methodology for optimizing energy and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bipartitioning and encoding in low-power pipelined circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems
ACM Transactions on Embedded Computing Systems (TECS)
Dynamic functional unit assignment for low power
The Journal of Supercomputing
Compilers for leakage power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interactive presentation: PowerQuest: trace driven data mining for power optimization
Proceedings of the conference on Design, automation and test in Europe
Performance and power consumption of computers using batch service with event and time counter
PDCN'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: parallel and distributed computing and networks
Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture
Journal of Signal Processing Systems
Resurrecting infeasible clock-gating functions
Proceedings of the 46th Annual Design Automation Conference
Scheduling with multiple voltages
Integration, the VLSI Journal
Want to save energy?: put intelligence into systems
CSECS'09 Proceedings of the 8th WSEAS International Conference on Circuits, systems, electronics, control & signal processing
Power optimization using dynamic power management
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Dynamic power reduction of FPGA-based reconfigurable computers using precomputation
ACM SIGARCH Computer Architecture News
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We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be "turned off" in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay.