Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A method of redundant clocking detection and power reduction at RT level design
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Challenges in clockgating for a low power ASIC methodology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automating RT-level operand isolation to minimize power consumption in datapaths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
Logic Synthesis and Verification
Logic Synthesis and Verification
Power Aware Design Methodologies
Power Aware Design Methodologies
Design for Testability of Gated-Clock FSMs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
Automatic ADL-based operand isolation for embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Intelligate: Scalable Dynamic Invariant Learning for Power Reduction
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
| Hi-index | 0.00 |
This paper describes a new automatic clock-gating extraction working at the RT-level. The key features of our approach are: (i) Seamless merging with existing industrial design flows and commercial tools; (ii) High scalability to deal with large circuits; (iii) Improved quality of results with respect to available commercial tools; (iv) Smaller and well-controled overhead in speed and area. Experimental results, on a set of industrial RTL designs, demonstrate the viability and practical impact of our approach.