Challenges in clockgating for a low power ASIC methodology

Clock-tree power optimization based on RTL clock-gating

Proceedings of the 40th annual Design Automation Conference

A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Power-aware clock tree planning

Proceedings of the 2004 international symposium on Physical design

Power minimization by clock root gating

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

Low-power gated and buffered clock network construction

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Type-matching clock tree for zero skew clock gating

Proceedings of the 45th annual Design Automation Conference

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP

HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers

Sub-row sleep transistor insertion for concurrent clock-gating and power-gating

PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation

Low-power anti-aging zero skew clock gating

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Fast power- and slew-aware gated clock tree synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems