Sub-row sleep transistor insertion for concurrent clock-gating and power-gating

Authors:
Karthikeyan Lingasubramanian;Andrea Calimera;Alberto Macii;Enrico Macii;Massimo Poncino
Affiliations:
Dipartimento di Automatica e Informatica, Politecnico di Torino,Torino, Italy;Dipartimento di Automatica e Informatica, Politecnico di Torino,Torino, Italy;Dipartimento di Automatica e Informatica, Politecnico di Torino,Torino, Italy;Dipartimento di Automatica e Informatica, Politecnico di Torino,Torino, Italy;Dipartimento di Automatica e Informatica, Politecnico di Torino,Torino, Italy
Venue:
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Year:
2011

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Abstract

Concurrent clock gating (CG) and power gating (PG) can help to tackle both static and dynamic power simultaneously, thereby enabling the design of low-power and energy efficient applications. Unfortunately the automatic integration of the two techniques in standard design flows is limited by several technical impediments. Among them, physical constraints during the Sleep Transistor Insertion (STI) imposed by rowbased layout rules are certainly the most critical. Although determining the feasibility of the whole clock-gating and power-gating (CG-PG) integration, the adopted STI methodology may have drastic effects on several circuit metrics, like operating frequency, throughput and power savings. In this paper we introduce a layout-friendly STI approach for fine-grained CG-PG inclusion. The proposed method, that is aware of the timing-driven strategies adopted by most of the commercial placer tools, allows sub-row insertion of independent sleep-transistor cells, therefore enabling finer resolution in the CG-PG integration, along with minimal cell displacement and negligible layout disruption. This enables a larger number of cells to be power-gated (i.e., larger potential power-savings w.r.t. state-of-the-art fine-grained STI strategies), without delay overhead. Experimental results, conducted on a set of circuit benchmarks mapped onto an industrial 65nm technology, indicate that more than 50% of the total number of cells can be clock- and power-gated simultaneously, without any speed degradation.