Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Active-mode leakage reduction with data-retained power gating
Proceedings of the Conference on Design, Automation and Test in Europe
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Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way that the clock-gating information can be used to drive the control signal of the power-gating circuitry, thus providing additional leakage minimization conditions w.r.t. those manually inserted by the designer. This conceptual integration, however, poses several challenges when moved to industrial design flows. Although both clock and power-gating are supported by most commercial synthesis tools, their combined implementation requires some flexibility in the back-end tools that is not currently available. This paper presents a layout-oriented synthesis flow which integrates the two techniques and that relies on leading-edge, commercial EDA tools. Starting from a gated-clock netlist, we partition the circuit in a number of clusters that are implicitly determined by the groups of cells that are clock-gated by the same register. Using a row-based granularity, we achieve runtime leakage reduction by inserting dedicated sleep transistors for each cluster. The entire flow has been benchmarked on a industrial design mapped onto a commercial, 65nm CMOS technology library.