Post-layout leakage power minimization based on distributed sleep transistor insertion

Authors:
Pietro Babighian;Luca Benini;Alberto Macii;Enrico Macii
Affiliations:
Politecnico di Torino, Torino, Italy;Universit á di Bologna, Bologna, Italy;Politecnico di Torino, Torino, Italy;Politecnico di Torino, Torino, Italy
Venue:
Proceedings of the 2004 international symposium on Low power electronics and design
Year:
2004

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Abstract

This paper introduces a new approach to sub-threshold leakage power reduction in CMOS circuits. Our technique is based on automatic insertion of sleep transistors for cutting sub-threshold current when CMOS gates are in stand-by mode. Area and speed overhead caused by sleep transistor insertion are tightly controlled thanks to: (i) a post-layout incremental modification step that inserts sleep transistors in an existing row-based layout; (ii) an innovative algorithm that selects the subset of cells that can be gated for maximal leakage power reduction, while meeting user-provided constraints on area and delay increase. The presented technique is highly effective and fully compatible with industrial back-end flows, as demonstrated by post-layout analysis on several benchmarks placed and routed with state-of-the art commercial tools for physical design.