Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Simultaneous Vt selection and assignment for leakage optimization
Proceedings of the 2003 international symposium on Low power electronics and design
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
On optimal physical synthesis of sleep transistors
Proceedings of the 2004 international symposium on Physical design
Experimental measurement of a novel power gating structure with intermediate power saving mode
Proceedings of the 2004 international symposium on Low power electronics and design
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage current estimation of CMOS circuit with stack effect
Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
A simple mechanism to adapt leakage-control policies to temperature
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Functionality directed clustering for low power MTCMOS design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Enabling fine-grain leakage management by voltage anchor insertion
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Charge recycling in MTCMOS circuits: concept and analysis
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Low-power fanout optimization using MTCMOS and multi-Vt techniques
Proceedings of the 2006 international symposium on Low power electronics and design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Proceedings of the 44th annual Design Automation Conference
Optimal sleep transistor synthesis under timing and area constraints
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A novel performance driven power gating based on distributed sleep transistor network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Enhanced leakage reduction techniques using intermediate strength power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An MTCMOS technology for low-power physical design
Integration, the VLSI Journal
A robust power gating structure and power mode transition strategy for MTCMOS design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleep transistor sizing and adaptive control for supply noise minimization considering resonance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Sleep transistor sizing for leakage power minimization considering temporal correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technique for controlling power-mode transition noise in distributed sleep transistor network
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Simultaneous Vtselection and assignment for leakage optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comprehensive analysis and control of design parameters for power gated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Genetic algorithm based fine-grain sleep transistor insertion technique for leakage optimization
ICNC'06 Proceedings of the Second international conference on Advances in Natural Computation - Volume Part I
Proceedings of the International Conference on Computer-Aided Design
A semiempirical model for wakeup time estimation in power-gated logic clusters
Proceedings of the 49th Annual Design Automation Conference
ACM Transactions on Architecture and Code Optimization (TACO)
Power-up sequence control for MTCMOS designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Off-path leakage power aware routing for SRAM-based FPGAs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Current density aware power switch placement algorithm for power gating designs
Proceedings of the 2014 on International symposium on physical design
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Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.