MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleep transistor sizing using timing criticality and temporal currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Functionality directed clustering for low power MTCMOS design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Monte Carlo approach for maximum power estimation based on extreme value theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal sleep transistor synthesis under timing and area constraints
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
Proceedings of the 13th international symposium on Low power electronics and design
A scalable algorithmic framework for row-based power-gating
Proceedings of the conference on Design, automation and test in Europe
Optimal MTCMOS reactivation under power supply noise and performance constraints
Proceedings of the conference on Design, automation and test in Europe
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
NBTI-aware sleep transistor design for reliable power-gating
Proceedings of the 19th ACM Great Lakes symposium on VLSI
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
NBTI-Aware Clustered Power Gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IR-drop analysis of graphene-based power distribution networks
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Sleep transistor insertion is a key step in low power design methodologies for nanometer CMOS. In the clustered sleep transistor approach, a single sleep transistor is shared among a number of gates and it must be sized according to the maximum current that can be injected onto the virtual ground by the gates in the cluster. A conservative (upper bound) estimate of the maximum injected current is required in order to avoid excessive speed degradation and possible violations of timing constraints. In this paper we propose a scalable algorithm for tightening upper bound computation, with a controlled and tunable computational cost. The algorithm leverages the capabilities of state-of-the-art commercial timing analysis engines, and it is tightly integrated into standard industrial flow for leakage optimization. Benchmark results demonstrate the effectiveness and efficiency of our approach.