MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleep transistor sizing using timing criticality and temporal currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Functionality directed clustering for low power MTCMOS design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A scalable algorithmic framework for row-based power-gating
Proceedings of the conference on Design, automation and test in Europe
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The use of sleep transistors as power-gating elements to cut-off sub-threshold leakage stand-by currents has become a very popular solution to tackle the rise of leakage energy consumption in nano-CMOS designs. One of the most critical challenges in sleep-transistor based power gating is the sizing of the sleep transistor, which mainly depends on the discharge current pattern over time of the set of cells that share a single sleep transistor. In this work we provide a sleep transistor clustering and sizing methodology that improves over previous solutions by (i) accounting for sleep transistor area constraints (thus implying the possibility of gating only a subset of the cells of the design), and (ii) by utilizing the temporal variations in discharge current pattern to achieve improved leakage power-savings. Experimental results on standard benchmarks show that we can achieve improvement in leakage power savings, compared to previous works, ranging from 12% to 17% on average, depending on the allowed area constraint.