Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Low power design challenges for the decade (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Low power design using dual threshold voltage
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe
Optimal sleep transistor synthesis under timing and area constraints
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
Proceedings of the 13th international symposium on Low power electronics and design
A scalable algorithmic framework for row-based power-gating
Proceedings of the conference on Design, automation and test in Europe
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Current density aware power switch placement algorithm for power gating designs
Proceedings of the 2014 on International symposium on physical design
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Multi-Threshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption. Sleep transistor sizing is the key issue when MTCMOS circuit is designed. If the sleep transistor size is too large, the circuit performance can be maintained but the dynamic power consumption of the sleep transistor will increase. On the other hand, if the sleep transistor size is too small, there will be significant performance degradation because of the increased resistance to ground. Previous approach [1, 2] designed the sleep transistor size based on mutual exclusive discharge patterns. However, these approaches considered only topology of a circuit. We observed that two possible simultaneous switching gates may not discharge at the same time in terms of functionality. Thus, we propose an algorithm to determine how to cluster cells to share sleep transistors taking both topology and functionality into consideration. The results show that the proposed method can achieve on the average 18% reduction ratio in terms of the number of sleep transistors as compared to the method without considering functionality.