Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Automated selective multi-threshold design for ultra-low standby applications
Proceedings of the 2002 international symposium on Low power electronics and design
On optimal physical synthesis of sleep transistors
Proceedings of the 2004 international symposium on Physical design
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Leakage control through fine-grained placement and sizing of sleep transistors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Sleep transistor sizing using timing criticality and temporal currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Functionality directed clustering for low power MTCMOS design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Enabling fine-grain leakage management by voltage anchor insertion
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
Introduction to Operations Research and Revised CD-ROM 8
Introduction to Operations Research and Revised CD-ROM 8
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Proceedings of the conference on Design, automation and test in Europe
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Proceedings of the 44th annual Design Automation Conference
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Leakage power has become a serious concern in nanometer CMOS technologies, and power-gating has shown to offer a viable solution to the problem with a small penalty in performance. This paper focuses on leakage power reduction through automatic insertion of sleep transistors for power-gating. In particular, we propose a novel, layout-aware methodology that facilitates sleep transistor insertion and virtual-ground routing on row-based layouts. We also introduce a clustering algorithm that is able to handle simultaneously timing and area constraints, and we extend it to the case of multi-Vt sleep transistors to increase leakage savings. The results we have obtained on a set of benchmark circuits show that the leakage savings we can achieve are, by far, superior to those obtained using existing power-gating solutions and with much tighter timing and area constraints.