Power and ground network topology optimization for cell based VLSIs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Enchanced multi-threshold (MTCMOS) circuits using variable well bias
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel performance driven power gating based on distributed sleep transistor network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: the min-area sleep transistor insertion (and sizing) (TIS) problem with respect to a fixed P/G network, and the simultaneous sleep transistor insertion and P/G network sizing (TIPGS) problem to minimize the weighted area of sleep transistors and P/G network. We show that there may exist multiple sleep transistor insertion solutions that all lead to a same minimum area in the TIS and TIPGS problems. We develop optimal algorithms to TIS and TIPGS problems by modeling the circuit as a single current source, and then extend to the case modeling the circuit as distributed current sources. Compared with the best known approach, our algorithms achieve area reduction by up to 44.1% and 61.3% for TIS and TIPGS, respectively.