Proceedings of the 39th annual Design Automation Conference
Introduction to Algorithms
Estimation of Maximum Power-up Current
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
On optimal physical synthesis of sleep transistors
Proceedings of the 2004 international symposium on Physical design
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 43rd annual Design Automation Conference
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Proceedings of the 44th annual Design Automation Conference
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
A robust power gating structure and power mode transition strategy for MTCMOS design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient on-line module-level wake-up scheduling for high performance multi-module designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Open systemc simulator with support for power gating design
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
Power-up sequence control for MTCMOS designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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During the power mode transition, simultaneously turning ON sleep transistors provides a sufficiently large surge current, which may cause a large IR drop in the power networks. The IR drop in turn causes errors in the retention sequential elements of the sleep modules or errors of the nonsleep modules. One efficient way to control the surge current is to schedule the turn-ON sequences of sleep transistors. In this paper, we introduce several important properties of the surge current during the power mode transition for the distributed sleep transistor network (DSTN) design, which is a popular power gating design style. Based on these properties, we propose an accurate estimation of the surge current and provide efficient schedules on the DSTN structure. Our methods achieved significantly better results than previous works--on average, 261 times wake-up time reduction and 30% less energy loss during the power mode transition.