On area/depth trade-off in LUT-based FPGA technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Maximum current estimation considering power gating
Proceedings of the 2001 international symposium on Physical design
Combinational Test Generation for Acyclic Sequential Circuits using a Balanced ATPG Model
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Execution cache-based microarchitecture power-efficient superscalar processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using SAT-based techniques in power estimation
Microelectronics Journal
Leakage current optimization techniques during test based on don't care bits assignment
Journal of Computer Science and Technology
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ILP based approach for input vector controlled (IVC) toggle maximization in combinational circuits
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-gated circuit must be brought to a valid state from the power-off state, when all nodes in the circuit are at logic zero state, before useful computation can begin. Thus, estimation of the maximum current in a power gated circuit must determine the maximum of all possible power-up and normal switching current. In this paper, we propose a cluster-based ATPG algorithm to estimate the maximum power-up current for combinational circuits. Our method achieves substantial improvement over simulation-based methods and also over the previously proposed ATPG-based methods. Further, we also formulate the sequential circuit maximum current problem as a combinational ATPG problem, and solve it using the cluster-based estimation algorithm. Experimental results show that the maximum power-up current for sequential circuits can be up to 73% larger than the maximum normal switching current.