Maximum current estimation in CMOS circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Resolving signal correlations for estimating maximum currents in CMOS combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Maximum power estimation for CMOS circuits using deterministic and statistic approaches
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Dynamic Power Management for Microprocessors: A Case Study
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Estimation of maximum power for sequential circuits considering spurious transitions
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of Maximum Power-up Current
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
High-level area and power-up current estimation considering rich cell library
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Optimal module and voltage assignment for low-power
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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As semiconductor technology scales down, the leakage power will soon become comparable to the dynamic power. To reduce both dynamic and leakage power, power gating in addition to clock gating should be used because clock gating saves only dynamic power. The knowledge of maximum current is needed to design high-performance and reliable circuits using power gating. However, all existing techniques for maximum current estimation are not applicable to power gating. In this paper, we study the maximum current estimation problem considering power gating. We develop two algorithms based on automatic test pattern generation (ATPG), and apply them to ISCAS'85 benchmarks. Experiments show that our new estimation algorithms can finish the largest benchmark circuit within ten seconds, and achieve up to 87% larger current when compared to an existing ATPG-based estimation algorithm that is able to obtain maximum current estimation 6% less than the theoretical maximum current without considering power gating. This implies that power gating may lead to a larger maximum current when compared to the normal maximum switching current, and open a new avenue for maximum current estimation as well as circuit reliability research.