Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Guarded evaluation: pushing power management to logic synthesis/design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Activity-driven clock design for low power circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
PowerPC 603, A Microprocessor for Portable Computers
IEEE Design & Test
Optimization of combinational and sequential logic circuits for low power using precomputation
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Modeling and automating selection of guarding techniques for datapath elements
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
New clock-gating techniques for low-power flip-flops
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Maximum current estimation considering power gating
Proceedings of the 2001 international symposium on Physical design
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC '02 Proceedings of the 11th International Conference on Compiler Construction
A sink-n-hoist framework for leakage power reduction
Proceedings of the 5th ACM international conference on Embedded software
Compilers for leakage power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compilation for compact power-gating controls
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing functional unit power consumption and its variation using leakage sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compiler analysis and supports for leakage power reduction on microprocessors
LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Power devil: tool for power gating strategy selection
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Estimation based power and supply voltage management for future RF-powered multi-core smart cards
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Dynamic power management is one of the most popular and successful low power design techniques in commercial integrated circuits, especially microprocessors. However, despite its significance, relatively little has been published about it. The purpose of this paper is to provide an open discussion of the application of dynamic power management for a real microprocessor. TORCH, a statically scheduled superscalar microprocessor, is chosen for this purpose. We describe several techniques that we classify as dynamic power management-techniques aimed at reducing the power wasted in unnecessary circuit activity in the design. Some of the techniques have been used before for low power designs. Some others are new and it is demonstrated that significant power savings are achieved with these as well. We provide design details to illustrate the application of instances of all dynamic power management techniques for TORCH. Using a combination of techniques, the power consumption is reduced by about 23%. We hope that this study would lead to a wider recognition of dynamic power management as a very effective and practical power reduction technique.