Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Architectural and compiler techniques for energy reduction in high-performance microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Compiler optimization on VLIW instruction scheduling for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Managing static leakage energy in microprocessor functional units
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Cache designs for energy efficiency
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Dynamic Power Management for Microprocessors: A Case Study
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Compiler Support for Reducing Leakage Energy Consumption
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Compilers for leakage power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Compiler analysis and supports for leakage power reduction on microprocessors
LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
The Journal of Supercomputing
Journal of Signal Processing Systems
Copy propagation optimizations for VLIW DSP processors with distributed register files
LCPC'06 Proceedings of the 19th international conference on Languages and compilers for parallel computing
Energy-aware code motion for GPU shader processors
ACM Transactions on Embedded Computing Systems (TECS)
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Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture and compiler solutions to employ power-gating mechanisms to reduce leakage power. This approach is to have compilers perform data-flow analysis and insert instructions at programs to shut down and wake up components whenever appropriate for power reductions. While this approach has been shown to be effective in early studies, there are concerns for the amount of power-control instructions being added to programs with the increasing amount of components equipped with power-gating control in a SoC design platform. In this paper, we present a Sink-N-Hoist framework in the compiler solution to generate balanced scheduling of power-gating instructions. Our solution will attempt to merge power-gating instructions as one compound instruction. Therefore, it will reduce the amount of power-gating instructions issued.We perform experiments by incorporating our compiler analysis and scheduling policies into SUIF compiler tools and by simulating the energy consumptions on Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further in reducing leakage power compared to previous methods.