A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On-Line Scheduling of Imprecise Computations to Minimize Error
SIAM Journal on Computing
Performance evaluation and prediction for parallel algorithms on the BBN GP1000
ICS '90 Proceedings of the 4th international conference on Supercomputing
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Dynamic voltage scaling on a low-power microprocessor
Proceedings of the 7th annual international conference on Mobile computing and networking
Energy priority scheduling for variable voltage processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Compiler optimization on VLIW instruction scheduling for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints
Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An HMAC processor with integrated SHA-1 and MD5 algorithms
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A sink-n-hoist framework for leakage power reduction
Proceedings of the 5th ACM international conference on Embedded software
Energy optimization for a two-device data flow chain
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A highly efficient AES cipher chip
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Compilers for leakage power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling for reduced CPU energy
OSDI '94 Proceedings of the 1st USENIX conference on Operating Systems Design and Implementation
Compiler analysis and supports for leakage power reduction on microprocessors
LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Power optimization of variable-voltage core-based systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Review: Energy-aware performance analysis methodologies for HPC architectures-An exploratory study
Journal of Network and Computer Applications
Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures
The Journal of Supercomputing
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Dynamic voltage scaling (DVS) and power gating (PG) have become mainstream technologies for low-power optimization in recent years. One issue that remains to be solved is integrating these techniques in correlated domains operating with multiple voltages. This article addresses the problem of power-aware task scheduling on a scalable cryptographic processor that is designed as a heterogeneous and distributed system-on-a-chip, with the aim of effectively integrating DVS, PG, and the scheduling of resources in multiple voltage domains (MVD) to achieve low energy consumption. Our approach uses an analytic model as the basis for estimating the performance and energy requirements between different domains and addressing the scheduling issues for correlated resources in systems. We also present the results of performance and energy simulations from transaction-level models of our security processors in a variety of system configurations. The prototype experiments show that our proposed methods yield significant energy reductions. The proposed techniques will be useful for implementing DVS and PG in domains with multiple correlated resources.