Performance evaluation and prediction for parallel algorithms on the BBN GP1000

Authors:
François Bodin;Daniel Windheiser;William Jalby;Daya Atapattu;Mannho Lee;Dennis Gannon
Affiliations:
Indiana University, IRISA Rennes and INRIA France;Indiana University, IRISA Rennes and INRIA France;Indiana University, IRISA Rennes and INRIA France;Department of Computer Science, Indiana University;Department of Computer Science, Indiana University;Department of Computer Science, Indiana University
Venue:
ICS '90 Proceedings of the 4th international conference on Supercomputing
Year:
1990

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Abstract

The techniques of “load/store” memory reference modeling is based on deriving performance characteristics of the memory architecture of a computer by looking at the behavior of simple sequences of load, store and nop (null operation) instructions. The resulting data base can be used to match load/store templates against algorithm kernels to predict performance or as a source of data for testing analytical models of the architecture. In this paper we study the BBN GP1000 parallel processing system. We show how to build a subset of the load/store kernels needed to characterize the machine and illustrate the behavior of a simple model based on the data.