Building analytical models into an interactive performance prediction tool
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System design methodologies for a wireless security processing platform
Proceedings of the 39th annual Design Automation Conference
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
IEEE Transactions on Software Engineering
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A hierarchical modeling framework for on-chip communication architectures
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An HMAC processor with integrated SHA-1 and MD5 algorithms
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Proceedings of the 43rd annual Design Automation Conference
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The customization of architectures in designing the security processor-based systems typically involves timeconsuming simulation and sophisticated analysis in the exploration of design spaces. In this paper, we present an analytical modeling strategy for synoptically exploring of the candidate architectures of security processor-based systems. of We demonstrate examples to employ our analytical models for design space explorations of embedded security systems to deal with scalability issues and architecture constraints. The experiments with the cycle-accurate simulation exhibit the applicability of analytical modeling: average prediction error is less than 10% while speed improvement is in several orders of magnitude.