Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
Object-oriented modeling and design
Object-oriented modeling and design
Design patterns: elements of reusable object-oriented software
Design patterns: elements of reusable object-oriented software
Pipelined memory shared buffer for VLSI switches
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
DAC '97 Proceedings of the 34th annual Design Automation Conference
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
SystemC: a modeling platform supporting multiple design abstractions
Proceedings of the 14th international symposium on Systems synthesis
Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
An Object-Oriented Communication Library for Hardware-Software CoDesign
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Parallelism in random access machines
STOC '78 Proceedings of the tenth annual ACM symposium on Theory of computing
Design Tools for Application Specific Embedded Processors
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast exploration of bus-based on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
System-level design space exploration for security processor prototyping in analytical approaches
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Exploiting TLM and object introspection for system-level simulation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Implementing DSP Algorithms with On-Chip Networks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Fast exploration of bus-based communication architectures at the CCATB abstraction
ACM Transactions on Embedded Computing Systems (TECS)
A cooperative universal data model platform for the data-centric electronic system-level design
Advanced Engineering Informatics
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Design of AXI bus based MPSoC on FPGA
ASID'09 Proceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
A method to remove deadlocks in networks-on-chips with wormhole flow control
Proceedings of the Conference on Design, Automation and Test in Europe
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
The Lotterybus on-chip communication architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient exploration of bus-based system-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CA-Ex: a tuning-incremental methodology for communication architectures in embedded systems
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
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The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication architecture should be included in any quantitative evaluation of system design during design space exploration. While there are several mature methodologies for the modeling and evaluation of architectures of processing elements, there is relatively little work done in modeling of an extensive range of on-chip communication architectures, and integrating this into a single modeling and simulation environment combining processing element and on-chip communication architectures. This paper describes a modeling framework with accompanying simulation tools that attempts to fill this gap. Based on an analysis of a wide range of on-chip communication architectures, we describe how a specific hierarchical class library can be used to develop new on-chip communication architectures, or variants of existing ones with relatively little incremental effort. We demonstrate this through three case studies including two commercial on-chip bus systems and an on-chip packet switching network. Here we show that through careful analysis and construction it is possible for the modeling environment to support the common features of these architectures as part of the library and permit instantiation of the individual architectures as variants of the library design. As part of this methodology we also show how different levels of abstraction of the model can be supported and viewed as different variants that can be used in an accuracy versus simulation time trade-off.