Scheduling with bus access optimization for distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
An Overview of Methodologies and Tools in the Field of System-Level Design
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
A hierarchical modeling framework for on-chip communication architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Architecture-level performance evaluation of component-based embedded systems
Proceedings of the 40th annual Design Automation Conference
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
Design space exploration for optimizing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The communication architecture (CA) problem is at the very heart of system level design related to the development of distributed embedded systems. The design of efficient CAs is pivotal because communication is becoming the most important source of on-chip desired performance numbers. In this paper we focus on the aspects of CA design in heterogeneous systems consisting of arbitrarily linked multi-components, and introduce a new design methodology named CA-Ex which enables a tuning-incremental architecture exploration. Unlike previous research efforts, CA-Ex employs three kinds of optimization strategies to implement topology, mapping and scheduling scheme, and interface circuits. One of the major contributions is that we summarily present four architecting scenarios and outline a unified framework to achieve a specification-modeling-exploration process. Finally, we evaluate CA-Ex through an illustrative case study on JPEG decoder and describe its advantages.