Field Programmable Communication Emulation and Optimization for Embedded System Design
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
CSCWD'06 Proceedings of the 10th international conference on Computer supported cooperative work in design III
CA-Ex: a tuning-incremental methodology for communication architectures in embedded systems
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
| Hi-index | 0.00 |
In this paper, we present an automated approach to communication architecture synthesis with real-time constraints. Based on a pre-partitioned hardware/software specification and given communication constraints a thorough analysis of different communication structures is carried out using performance models of communication links to determine optimized communication architecture. The complete hardware/software system will be emulated as an architecture-precise prototype on a real-time platform to verify the derived communication architecture as well as the hardware/software partitioning