Synthesis of system-level communication by an allocation-based approach
ISSS '95 Proceedings of the 8th international symposium on System synthesis
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Readings in Hardware/Software Co-Design
Readings in Hardware/Software Co-Design
A Hardware-Software Real-Time Operating System Framework for SoCs
IEEE Design & Test
Modeling Real-Time Systems-Challenges and Work Directions
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
A hierarchical modeling framework for on-chip communication architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
Synchronization protocols in distributed real-time systems
ICDCS '96 Proceedings of the 16th International Conference on Distributed Computing Systems (ICDCS '96)
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Networks on chip
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Packetized On-Chip Interconnect Communication Analysis for MPSoC
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Layered, Multi-Threaded, High-Level Performance Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Integrating communication protocol selection with hardware/software codesign
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Complete Network-On-Chip Emulation Framework
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Software-directed combined cpu/link voltage scaling fornoc-based cmps
SIGMETRICS '08 Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Trace-driven workload simulation method for Multiprocessor System-On-Chips
Proceedings of the 46th Annual Design Automation Conference
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A high-performance low-power ethernet controller with embedded 8-bit MCU for information appliances
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Combining mapping and partitioning exploration for NoC-based embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Embedded Systems Design
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With the increasing number of transistors available ona single chip, the System-on-Chip (SoC) paradigm hasevolved to exploit its full potential. As many processorscan be accommodated on a single chip, this paradigmhas forced a communication-centric, as opposed to acomputation-centric, design view. Thus, the choice, managementand modeling of the SoC interconnect is essentialfor an accurate evaluation and optimization of the globalperformance of a system. Recently, the notion of Network-on-Chip (NoC) has been introduced as a way to extend theclassical bus-based interconnection, which is still the dominantinterconnect structure for SoC's, into a dedicated, segmentedand, possibly, packet-switched network fabric [2].In this paper, we present a NoC model which, together witha multiprocessor real-time operating system (RTOS) model,allows us to model and analyze the behavior of a complexsystem that has a real-time application running on amultiprocessor platform. We demonstrate the potential ofour model by simulating and analyzing a small multiprocessorsystem connected through different NoC topologies,and discus how the simulation model may be used duringthe design-space exploration phase.