Software performance estimation strategies in a system-level design tool
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Reliable estimation of execution time of embedded software
Proceedings of the conference on Design, automation and test in Europe
A framework for evaluating design tradeoffs in packet processing architectures
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
Schedulers as model-based design elements in programmable heterogeneous multiprocessors
Proceedings of the 40th annual Design Automation Conference
High-level algorithmic complexity evaluation for system design
Journal of Systems Architecture: the EUROMICRO Journal
Network-on-Chip Modeling for System-Level Multiprocessor Simulation
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Unified Component Integration Flow for Multi-Processor SoC Design and Validation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fine-grained application source code profiling for ASIP design
Proceedings of the 42nd annual Design Automation Conference
SHAPES:: a tiled scalable software hardware architecture platform for embedded systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
HySim: a fast simulation framework for embedded software development
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Fast cycle-approximate instruction set simulation
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Applying neural networks to performance estimation of embedded software
Journal of Systems Architecture: the EUROMICRO Journal
SciSim: a software performance estimation framework using source code instrumentation
WOSP '08 Proceedings of the 7th international workshop on Software and performance
MAPS: an integrated framework for MPSoC application parallelization
Proceedings of the 45th annual Design Automation Conference
Cycle-approximate retargetable performance estimation at the transaction level
Proceedings of the conference on Design, automation and test in Europe
Efficient implementation of native software simulation for MPSoC
Proceedings of the conference on Design, automation and test in Europe
Evaluation of ASIPs Design with LISATek
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Processor Description Languages
Processor Description Languages
A high-level virtual platform for early MPSoC software development
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Native MPSoC co-simulation environment for software performance estimation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
An efficient approach for system-level timing simulation of compiler-optimized embedded software
Proceedings of the 46th Annual Design Automation Conference
Trace-driven workload simulation method for Multiprocessor System-On-Chips
Proceedings of the 46th Annual Design Automation Conference
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Performance modeling of parallel applications on MPSoCs
SOC'09 Proceedings of the 11th international conference on System-on-chip
Software performance simulation strategies for high-level embedded system design
Performance Evaluation
Performance modeling of embedded applications with zero architectural knowledge
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
TLM automation for multi-core design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
System-level development of embedded software
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
QUAD: a memory access pattern analyser
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Statistical Performance Modeling in Functional Instruction Set Simulators
ACM Transactions on Embedded Computing Systems (TECS)
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Fast and accurate cache modeling in source-level simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate source-level simulation of embedded software with respect to compiler optimizations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The increasing demands of high-performance in embedded applications under shortening time-to-market has prompted system architects in recent time to opt for Multi-Processor Systems-on-Chip (MP-SoCs) employing several programmable devices. The programmable cores provide a high amount of flexibility and reusability, and can be optimized to the requirements of the application to deliver high-performance as well. Since application software forms the basis of such designs, the need to tune the underlying SoC architecture for extracting maximum performance from the software code has become imperative.In this paper, we propose a framework that enables software development, verification and evaluation from the very beginning of MP-SoC design cycle. Unlike traditional SoC design flows where software design starts only after the initial SoC architecture is ready, our framework allows a co-development of the hardware and the software components in a tightly coupled loop where the hardware can be refined by considering the requirements of the software in a stepwise manner. The key element of this framework is the integration of a fine-grained software instrumentation tool into a System-Level-Design (SLD) environment to obtain accurate software performance and memory access statistics. The accuracy of such statistics is comparable to that obtained through Instruction Set Simulation (ISS), while the execution speed of the instrumented software is almost an order of magnitude faster than ISS. Such a combined design approach assists system architects to optimize both the hardware and the software through fast exploration cycles, and can result in far shorter design cycles and high productivity. We demonstrate the generality and the efficiency of our methodology with two case studies selected from two most prominent and computationally intensive embedded application domains.