A compilation-based software estimation scheme for hardware/software co-simulation
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
RTOS Modeling for System Level Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System-level design flow based on a functional reference for HW and SW
Proceedings of the 44th annual Design Automation Conference
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A high-level virtual platform for early MPSoC software development
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Native MPSoC co-simulation environment for software performance estimation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Formal semantics for PSL modeling layer and application to the verification of transactional models
Proceedings of the Conference on Design, Automation and Test in Europe
A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot
Proceedings of the Conference on Design, Automation and Test in Europe
Accurately timed transaction level models for virtual prototyping at high abstraction level
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Efficient and precise simulation models at a high abstraction level are required in order to perform early design validations and architecture explorations of Multi-Processor System-On-Chip (MPSoC) platforms. Although native software simulation approaches provide interesting capabilities, they quickly become unsuitable when complex hardware architecture have to be considered. In this paper, we present a SystemC-based MPSoC platform implementation that allows native software simulation while keeping details of the underlying hardware model. The key contribution of this work is a realistic memory mapping modelling that makes possible the simulation of Operating Systems and software applications on complex hardware models with multiple processors and DMA devices. This method also allows the reuse of different software components for the target processor(s). Experimental results show the efficiency of the proposed method to validate software on complex hardware architectures.