Transaction level modeling: flows and use models
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
High-performance timing simulation of embedded software
Proceedings of the 45th annual Design Automation Conference
Efficient implementation of native software simulation for MPSoC
Proceedings of the conference on Design, automation and test in Europe
Using a dataflow abstracted virtual prototype for HdS-design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
TLM+ modeling of embedded HW/SW systems
Proceedings of the Conference on Design, Automation and Test in Europe
Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Analytical timing estimation for temporally decoupled TLMs considering resource conflicts
Proceedings of the Conference on Design, Automation and Test in Europe
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Transaction level modeling (TLM) improves the simulation performance by raising the abstraction level. In the TLM 2.0 standard based on OSCI SystemC, a single transaction can transfer a large data block. Due to such high abstraction, a great amount of information becomes invisible and thus timing accuracy can be degraded heavily. We present a methodology to accurately time such block transactions and achieve high simulation performance at the same time. First, before abstraction, a profiling process is performed on an instruction set simulator (ISS). Driver functions that implement the transfer of the data blocks are simulated. Several techniques are employed to trace the exact start and end of the driver functions as well as HW usages. Thus, a profile library of those driver functions can be constructed. Then, the application programs are host-compiled and use a single transaction to transfer a data block. A strategy is presented that efficiently estimates the timing of block transactions based on the profile library. It is the first method that takes into account caching effects that influence the timing of block transactions. Moreover, it ensures overall timing accuracy when integrated in other SW timing tools for full system simulation. Experimental results show that the block transactions are accurately timed, with average error less than 1%. At the same time, the simulation gain can be up to three orders of magnitude.