Fast and accurate transaction level models using result oriented modeling
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Shared resource access attributes for high-level contention models
Proceedings of the 44th annual Design Automation Conference
Native MPSoC co-simulation environment for software performance estimation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
TLM+ modeling of embedded HW/SW systems
Proceedings of the Conference on Design, Automation and Test in Europe
SystemQ: a queuing-based approach to architecture performance evaluation with systemc
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Accurately timed transaction level models for virtual prototyping at high abstraction level
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Fast cache simulation for host-compiled simulation of embedded software
Proceedings of the Conference on Design, Automation and Test in Europe
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Transaction level models (TLMs) can use temporal decoupling to increase the simulation speed. However, there is a lack of modeling support to time the temporally decoupled TLMs. In this paper, we propose a timing estimation mechanism for TLMs with temporal decoupling. This mechanism features an analytical model and novel delay formulas. Concepts such as resource usage and availability are used to derive the delay formulas. Based on them, a fast scheduling algorithm resolves resource conflicts and dynamically determines the timing of concurrent transaction sequences. Experiments show that the delay estimation formulas are capable of capturing the timing effects of resource conflicts. At the same time, the overhead of the scheduling algorithm is very low, hence the simulation speed remains high.