Data networks
LoPC: modeling contention in parallel algorithms
PPOPP '97 Proceedings of the sixth ACM SIGPLAN symposium on Principles and practice of parallel programming
A compilation-based software estimation scheme for hardware/software co-simulation
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Software performance estimation strategies in a system-level design tool
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems
Proceedings of the conference on Design, automation and test in Europe
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Event-based re-training of statistical contention models for heterogeneous multiprocessors
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Analytical timing estimation for temporally decoupled TLMs considering resource conflicts
Proceedings of the Conference on Design, Automation and Test in Europe
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Emerging single-chip heterogeneous multiprocessors feature hundreds of design elements contending for shared resources, making it difficult to isolate performance impacts of individual design changes. This work is the first to parameterize shared resource accesses in the form of access attributes, summarizing the impact of shared resource contention on system performance, analogous to the way RTL parameters summarize more detailed transistor models. The intuition behind access attributes is that much application and architecture dependent contention information is known during detailed cycle-accurate simulations, and would be useful to inform a higher level model. The detailed contention information is sampled from a short cycle-accurate simulation, "training" a high-level statistical regression model of contention. This contention model can then be used in simulation to estimate the impact of shared resource accesses at a high level of abstraction, enabling the designers to explore contention-related performance impacts of design decisions. Using the access attribute-based contention models resulted in speedups of 40X over cycle-accurate simulation, with average simulation errors of less than 1% with 95% confidence intervals of about ±3%.